Magnetoresistive Random Access Memory (MRAM), based on the integration of silicon CMOS with MTJ technology, is a major emerging technology that is highly competitive with existing semiconductor memories such as SRAM, DRAM, Flash, etc. A MRAM device is generally comprised of an array of parallel first conductive lines on a horizontal plane, an array of parallel second conductive lines on a second horizontal plane spaced above and formed in a direction perpendicular to the first conductive lines, and an MTJ (memory) element interposed between a first conductive line and a second conductive line at each crossover location. A first conductive line may be a word line while a second conductive line is a bit line or vice versa. Alternatively, a first conductive line may be a bottom electrode that is a sectioned line while a second conductive line is a bit line (or word line). There are typically other devices including transistors and diodes below the array of first conductive lines as well as peripheral circuits used to select certain MRAM cells within the MRAM array for read or write operations. A high speed version of MRAM architecture consists of a cell with an access transistor and a MTJ (1T1MTJ) in the array.
A MTJ element may be based on a tunneling magneto-resistance (TMR) effect wherein a stack of layers has a configuration in which two ferromagnetic layers are separated by a thin non-magnetic dielectric layer. In a MRAM device, the MTJ element is formed between a bottom electrode such as a first conductive line and a top electrode which is a second conductive line. A MTJ stack of layers that is subsequently patterned to form a MTJ element may be formed in a so-called bottom spin valve configuration by sequentially depositing a seed layer, an anti-ferromagnetic (AFM) pinning layer, a ferromagnetic “pinned” layer, a thin tunnel barrier layer, a ferromagnetic “free” layer, and a capping layer. In a MRAM MTJ, the free layer has traditionally been made of NiFe because of its reproducible and reliable switching characteristics as demonstrated by a low switching field (Hc) and low switching field uniformity (σHc).
The pinned layer has a magnetic moment that is fixed in the “y” direction, for example, by exchange coupling with the adjacent AFM layer that is also magnetized in the “y” direction. The free layer has a magnetic moment that is either parallel or anti-parallel to the magnetic moment in the pinned layer. The tunnel barrier layer is thin enough that a current through it can be established by quantum mechanical tunneling of conduction electrons. The magnetic moment of the free layer may change in response to external magnetic fields and it is the relative orientation of the magnetic moments between the free and pinned layers that determines the tunneling current and therefore the resistance of the tunneling junction. When a sense current is passed from the top electrode to the bottom electrode in a direction perpendicular to the MTJ layers, a lower resistance is detected when the magnetization directions of the free and pinned layers are in a parallel state (“1” memory state) and a higher resistance is noted when they are in an anti-parallel state or “0” memory state.
A high performance MRAM MTJ element is characterized by a high tunneling magnetoresistive (TMR) ratio also referred to as MR ratio where MR is the resistance change as a result of switching from a low resistance state (Rp) to a high resistance state (Rap) and expressed as the ratio (Rap−Rp)/Rp. Other MTJ parameters that are important for MRAM performance are low bit-to-bit resistance variation, low number of shorted bits, and low bit-to-bit switching current (or field) variation. Simultaneous optimization of all the aforementioned parameters is necessary for making high performance MRAM products that should have high reading margin, high writing margin, and lower error counts. Higher MR ratio and lower bit-to-bit resistance variation are necessary for high reading margin. Writing margin is more complicated and depends on many factors including magnetic free layer (coercivity and anisotropy energy), MTJ shape and size, and distance between the overlying word line/bit line and the free layer in the MTJ.
Numerous MTJ designs have been proposed and fabricated in the prior art but there is still a need for improvement in all of the performance categories mentioned above. Typically, an improvement in one property leads to a degradation in one or more other parameters. For example, NiFe affords excellent switching properties but the TMR ratio with a MTJ having a NiFe free layer is lower than can be achieved with CoFe, CoFeB, or other free layer materials. In addition, recent developments show that a MgO/CoFeB tunnel barrier/free layer configuration exhibits very high MR ratio (>200%) but this structure could not be directly applied in MRAM because a MTJ with a CoFeB free layer shows very poor writing margin (wide bit-to-bit switching current) due to its high anisotropy energy. Moreover, a high switch current is needed because of high coercivity associated with a CoFeB free layer. Even a CoFeB/NiFe composite free layer no longer exhibits a high MR characteristic of MgO/CoFeB configurations because the NiFe layer with fcc (111) crystal structure prevents the adjacent CoFeB layer from crystallizing in the bcc (001) phase necessary for high spin polarization (and thus high MR ratio) at the MgO/CoFeB interface.
U.S. Pat. No. 7,808,027 discloses a composite free layer with a NiFeCo/NiFe/NiFeHf configuration that is designed to provide a MR ratio of about 50%, high read margin, and low magnetostriction (λs).
U.S. Patent Application Publication 2010/0261295 teaches a free layer composite represented by Fe/amorphous CoFeB/Fe to achieve a low Gilbert damping constant, low critical current, high MR ratio, and low bit-to-bit resistance variation for a STT-MRAM application.
In U.S. Pat. No. 7,663,131, a MTJ is disclosed that has a CoFeB/CoFe AP1 layer and a NiFe/NiFeHf free layer to minimize error count (EC) while achieving high MR ratio, low magnetostriction, and a RA value of about 1100 ohm-um2 for 1 Mbit MRAM devices.
U.S. Pat. No. 7,479,394 describes a MgO tunnel barrier formation process where a first Mg layer is subjected to a radical oxidation step. Then a second Mg layer is deposited and a natural oxidation process is performed.
U.S. Patent Application Publication 2011/0086439 teaches a MgO fabrication sequence wherein a Mg layer is first treated with plasma etching to thin the metal layer and is then subjected to a radical oxidation step. Finally, a Mg cap is deposited on the oxidized first Mg layer.
In spite of all recent advancements in optimizing a MTJ for MRAM, an improved MTJ is still required that improves read margin and write margin without compromising other important MTJ parameters including bit line shorting and switching properties and a high TMR ratio.